While Moore�s law scaling continues to double transistor density every\r\ntechnology generation, new design challenges are introduced. One of these challenges is\r\nvariation, resulting in deviations in the behavior of transistors, most importantly in switching\r\ndelays. These exaggerated delays widen the gap between the average and the worst case\r\nbehavior of a circuit. Conventionally, circuits are designed to accommodate the worst case\r\ndelay and are therefore becoming very limited in their performance advantages. Thus,\r\nallowing for an average case oriented design is a promising solution, maintaining the pace of\r\nperformance improvement over future generations. However, to maintain correctness, such\r\nan approach will require on the fly mechanisms to prevent, detect, and resolve violations.\r\nThis paper explores such mechanisms, allowing the improvement of circuit performance\r\nunder intensifying variations. We present speculative error detection techniques along with\r\nrecovery mechanisms. We continue by discussing their ability to operate under extreme\r\nvariations including sub-threshold operation. While the main focus of this survey is on circuit approaches, for its completeness, we discuss higher-level, architectural and algorithmic\r\ntechniques as well.
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